A Comparative Design and Analysis of RISC-V Core
Author(s): 1. Dr. Arokia Priya Charles, 2. Abhiram Deshmukh
Authors Affiliations:
- Head of Department, Department of Semiconductor Engineering, D Y Patil International University, Pune, India.
- Student, Department of Electronics and Telecommunication, Dr. D Y Patil Institute of Engineering, Management and Research, Pune, India
This work presents a comparative design and analysis of two RISC-V processor architectures: a single-cycle RV32I core and a five-stage pipelined core. The single-cycle design establishes a baseline implementation, while the pipelined version integrates instruction fetch, decode, execute, memory, and write-back stages along with hazard detection, data forwarding, and branch resolution mechanisms. Both processors are described in RTL and synthesized on an FPGA platform using a unified workflow based on open-source EDA tools, ensuring accessibility and reproducibility of results.
Performance is assessed using the Embench-IoT benchmark suite, which provides realistic workloads representative of embedded and IoT domains. Key metrics such as Cycles per Instruction (CPI), maximum achievable clock frequency, FPGA resource consumption (LUTs, flip-flops, and memory blocks), and relative design complexity are measured. The analysis highlights the quantitative trade-offs between architectural simplicity and throughput, while also demonstrating the viability of open-source tool chains for advanced processor design and verification. This work thus provides practical insight into processor architecture evaluation and encourages the adoption of open-source methodologies in resource-constrained embedded system design.
Dr. Arokia Priya Charles, Abhiram Deshmukh (2025); A Comparative Design and Analysis of RISC-V Core, International Journal for Innovative Research in Multidisciplinary Field, ISSN(O): 2455-0620, Vol-11, Issue-12, Pp. 204-209. Available on – https://www.ijirmf.com/
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