30, October 2025

STA-aware Logic Optimization: Gate Sizing, Retiming and Buffering for Timing Closure in Standard-Cell ASIC Flows

VOLUME-11; ISSUE-10; OCT-2025

Author(s): PREETHA KAMATH B.

Authors Affiliations:

Ms.Preetha Kamath B

  Assistant professor , Electronics and Communication Engineering, KS Institute of Technology, Bangalore, India

 

DOIs:10.2015/IJIRMF/202510005     |     Paper ID: IJIRMF202510005


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This project investigates timing-driven optimization techniques in digital ASIC design: gate sizing, retiming, and buffer insertion. The goal is to create an STA-aware optimization flow that improves timing (meeting setup/hold), while keeping area and power within acceptable bounds. The work uses open-source EDA tools (Yosys for synthesis, OpenSTA for static timing analysis, and OpenROAD components or custom scripts) and standard benchmark circuits (ISCAS85/89 and small custom designs). The paper will implement algorithmic heuristics for sizing and retiming, apply them to benchmarks, document SDC constraints, run STA, and report improvements with quantitative analysis.By completing of this, the paper describes formulation of SDC constraints for real designs and use STA tools (OpenSTA) to extract timing violations and implementation and evaluate gate-sizing and retiming algorithms that consider setup/hold and cell drive strengths. The quantification of trade-offs between timing, area, and power; generate detailed reports and documentation in order to demonstrate the full ASIC standard-cell flow for a chosen design using open-source tools is carried out[1]-[4].

static timing analysis,gate sizing, retiming, and buffer insertion

Preetha Kamath B. (2025); STA-aware Logic Optimization: Gate Sizing, Retiming and Buffering for Timing Closure in Standard-Cell ASIC Flows, International Journal for Innovative Research in Multidisciplinary Field, ISSN(O): 2455-0620, Vol-11, Issue-10, Pp. 35-43.          Available on –   https://www.ijirmf.com/

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